By Dimitris Gizopoulos
This is a brand new form of edited quantity within the Frontiers in digital trying out publication sequence dedicated to contemporary advances in digital circuits trying out. The e-book is a finished elaboration on very important subject matters which trap significant study and improvement efforts at the present time. "Hot" themes of present curiosity to check expertise neighborhood were chosen, and the authors are key participants within the corresponding topics.
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Extra resources for Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
There is no metal etch to provide a slurry of particles. As a result, additional defect mechanisms become important. Figure 1-5 summarizes the processing differences. Note that the process is highly simplified when copper is used. In addition to a metal etch, aluminum processing also features two via/wire interfaces (tungsten to aluminum). Copper has only a single via/wire interface, since both vias and wires are deposited together. The absence of the metal etch and the reduced number of interfaces can result in a lower defect level for copper metalization than aluminum.
Let us look in more detail at the former. These have the property that they result in timing related failures at low operating frequency, but not high frequency. Originally, bridging faults were considered to have zero resistance. Later resistance models were added. Now, defect capacitance must also be considered. Intuitively, the increasing importance of wire capacitance in delay calculations is due to the increasing relative capacitance of wiring versus gates as a result of CMOS scaling. In order to measure timing behavior accurately, parasitic capacitances between wires must now be extracted for almost all designs.
Other open failures at 130nm and below behave similarly to those in previous generations, and similar detection methods apply, with the exception of CMP scratches, which produce complex patterns of shorts and opens, although these are usually readily detectable in logic and do not require specific ATPG. 9 The “Shmoo” was originally a blob-like character in the comic strip “Li’l Abner” The patterns of passing and failing tests in a Shmoo plot were reminiscent of its shape. 9 40 50 60 70 (b) Figure 1-19: Voltage versus timing shmoos at (a) 85oC and (b) 25oC showing copper void behavior.
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing) by Dimitris Gizopoulos